Design of a Phase Locked Loop by using 50nm CMOS Technology

Abstract

Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz. This thesis contains discrete components involving the Phase Detector and Voltage Controlled Oscillator and Filter. The Phase Detector and the Voltage Controlled Oscillator are designed with 50nm CMOS technology. The Filter is designed with microstrip transmission line. The Phase Detector, Voltage Controlled Oscillator and Band Pass Filter are designed and simulated using the softwares - LTSPICE, HSPICE, ADS. The simulated results are in good agreement. Process Scattering and Temperature variation have been applied in this thesis.