Simulation and Characterization of Silicon-On- Insulator (SOI) MOSFET

Abstract

During micro-electronic evolution, MOS Technology on massive substrate played a critical task. The regular reduction of transistors sizes leads us today’s nanoscale devices. According to the ITRS roadmap, the high performance device should have a much reduced gate length in the coming years. With this reduction, some parasitic physical effects became mostly amplified, leading to the end of MOSFETs technology on massive substrate. Bulk silicon CMOS processes are reaching their limit in device miniaturization and fabrication, new technologies, such as SOI technology gives a good alternative to that miniaturization. SOI technology allows the reduction of short channel effects that appear in nanoscale devices and also allows micro-electronic evolution to continue. In this paper, we present the simulation of SOI MOSFET structure obtained using SILVACO TCAD. We also exhibit some insights on the influence of some device parameters such as oxide length, doping, channel length etc on the drain current of SOI MOSFET.