| dc.contributor.author |
Raisa, Farah |
|
| dc.contributor.author |
Mansur, Anika Bintey |
|
| dc.contributor.author |
Ahmed, Tasmia |
|
| dc.date.accessioned |
2015-06-30T06:04:40Z |
|
| dc.date.available |
2015-06-30T06:04:40Z |
|
| dc.date.issued |
2013-12 |
|
| dc.identifier.uri |
http://hdl.handle.net/123456789/132 |
|
| dc.description |
First of all, we would like to thank The Almighty Allah for the accomplishment of our research
work. We would like to acknowledge and proclaim out gratitude to our thesis supervisor, Dr.
Md. Kawsar Alam, Assistant Professor, Department of EEE, BUET, for his valuable guidance
and advice. He inspired us greatly to work in the difficult field of high frequency analog domain.
He was always spontaneous to provide a helping hand whenever we were in a spot of bother. His
encouragement, guidance and support from the initial to the final level enabled us to develop an
understanding of the subject. Besides, we would like to thank the faculty members of the
Department of Electrical Electronic and Communication Engineering, Military Institute of
Science and Technology for providing us with all kinds of support. We are indebted to the
authority of Military Institute of Science and Technology for providing us necessary funding and
good environment and facilities to complete this thesis paper.
Lastly we would like to thank every single individual who directly and indirectly helped us to
accomplish our thesis by providing advice, care, attention and all kinds support. |
en_US |
| dc.description.abstract |
During micro-electronic evolution, MOS Technology on massive substrate played a critical task.
The regular reduction of transistors sizes leads us today’s nanoscale devices. According to the
ITRS roadmap, the high performance device should have a much reduced gate length in the
coming years. With this reduction, some parasitic physical effects became mostly amplified,
leading to the end of MOSFETs technology on massive substrate. Bulk silicon CMOS processes
are reaching their limit in device miniaturization and fabrication, new technologies, such as SOI
technology gives a good alternative to that miniaturization. SOI technology allows the reduction
of short channel effects that appear in nanoscale devices and also allows micro-electronic
evolution to continue. In this paper, we present the simulation of SOI MOSFET structure
obtained using SILVACO TCAD. We also exhibit some insights on the influence of some device
parameters such as oxide length, doping, channel length etc on the drain current of SOI
MOSFET. |
en_US |
| dc.description.sponsorship |
Department of Electrical, Electronic & Communication Engineering
Military Institute of Science and Technology (MIST) |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
Department of Electrical, Electronic & Communication Engineering, Military Institute of Science and Technology (MIST) |
en_US |
| dc.relation.ispartofseries |
Bachelor thesis in Electrical, Electronic and Communication Engineering.; |
|
| dc.subject |
Simulation, Characterization, Silicon-On-Insulator, MOSFET. |
en_US |
| dc.title |
Simulation and Characterization of Silicon-On- Insulator (SOI) MOSFET |
en_US |
| dc.type |
Thesis |
en_US |
