Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology

Abstract

This thesis paper comprises the study and performance analysis of four full adders with various topologies. Propagation delay, power dissipation and power delay product are the parameters to measure the performance of full adders. The overall performance can be improved by reducing power and delay which is done by optimizing the transistor size. For meeting the demands of tech-savvy fast progressing world of electronics, the sole focus for adder architecture is on making it more efficient. The design and simulation is carried out for four full adders (Conventional, transmission gate, 14T & GDI based technique) for transistor count, power dissipation, delay and power delay products. It is performed in virtuoso platform, using Cadence tool with available GPDK –90nm kit having MOS Capacitance value of 50 femto farad. The width of NMOS and PMOS is 120nm and 240nm respectively. Delay estimation is obtained by taking the average propagation delay. Transmission gate full adder has sheer advantage of high speed but consumes more power. On the other hand, GDI full adder gives reduced voltage swing not being able to pass logic 1 and logic 0 completely showing degraded output. Transmission gate full adder shows better performance in terms of delay, whereas 14T full adder shows better performance considering overall factors.