Abstract:
Phase-Locked Loop (PLL) based frequency synthesizer is one of the most crucial
components in mobile or wireless communications. It is mainly used for frequency
multiplication with the help of a PLL. With the development of RFICs in the wireless
communication sector, researchers are trying their best to improve IC’s specifications.
Their main concerns are area and power consumption. So for a highly efficient frequency synthesizer design, a highly efficient PLL is required to sustain this challenge.
The main focus of this thesis work is to design a PLL that is comprised of voltage
controlled oscillator (VCO), charge pump with low pass filter (LPF), phase-frequency
detector (PFD), and frequency divider (FD) in such a way that the circuit consumes
less power as well as require a small area.
In this thesis, a power-efficient LC VCO model for D band wireless applications
in 90 nm CMOS technology is developed and presented. An area-efficient design of
the proposed model is ensured by avoiding the requirement of additional capacitor for
an LC tank and varactor utilizing the parasitic capacitance of MOSs. An oscillation
frequency of (163.25 − 172.77)GHz is obtained with the applied tuning voltage while
it consumes a low DC power (2.822.96)mW. The proposed VCO provides relatively
high output power on its differential terminal and the simulated phase noise varies
from −92.99dBc/Hz to −75.81dBc/Hz. Additionally, an area-efficient and low
phase noise charge pump, frequency divider and, two GDI (Gate Diffusion Input) cells
based simple PFD have been developed and presented in this thesis. For charge pump
design, instead of using an op-amp, the cascade technique is applied to reduce current mismatch, nonlinear effect, and complicity. The proposed charge pump occupied
275.28µm 2 silicon area in layout design with dc power consumption 34.1µW from the
supply voltage of 1V. This simple structured PFD dissipates layout area of 26.95µm 2
and it consumes DC power of 2.391fW. The Dynamic D FF FDs dissipated layout
area and DC power are 101.74µm 2 and 4153.893nW respectively. Finally, from the
post-layout simulation for each design, it is found that the parasitic components didn't
change the circuit performances drastically from the schematic based simulations.
